Home   Homebrew Stuff  

A Bipolar Small Signal RF Amplifier

KB1LQC set out to build a 28 Mhz oscillator, which will eventually drive some 5v CMOS logic.  Since his oscillator circuit generates only about 50 mv of output, a following buffer amplifier is needed.  His first attempt to make this amplifier, using a 2N3904 in a common emitter configuration, was unsatisfactory and he asked for ideas on the QRZ forum.  This caught my attention and I set out to solve the problem. 

KB1LQC attempted to use the 2N3906 because that was what he had on hand.  I had a 2N2222 on hand, so I used that.  The general goal is to amplify a 50 mv pk-pk 28Mhz signal into a 5 volt pk-pk signal that swings from 0 to 5 volts - while introducing minimal distortion, of course.   

Based generally on component values that had bubbled up in the discussion on QRZ, here's the first circuit I built.

This circuit produces a highly distorted 2 volt pk-pk output, so it fails miserably.  The distortion is mostly caused by the loading of the source, which varies wildly in non-linear fashion as the signal varies.  The equivalent impedance looking into the base is mostly the impedance the emitter sees multiplied by the transistor's beta.  The impedance of the bypassed emitter resistor is quite low, probably an ohm or so at 28Mhz.  So the impedance at the base is maybe 100 ohms plus any non-linear behavior of the transistor.  This heavy and uneven loading of the source produces a distorted waveform.  If the source was perfect - if it truly had zero resistance - there would not be any distortion.

So I put an emitter follower between the source and the input of the amplifier.  This helped, but I still couldn't get more than a couple of volts of out at 10 Mhz, and way less at 28 Mhz.  At this point I gave up on the 2N2222 and switched to a PN5179.

Here's why:  the 2N2222 has a gain bandwidth (fT) of about 250-300.  This means that the beta at 28 Mhz is only going to be on the order of 10.  The PN5179, on the other hand, has a typical gain bandwidth of 2Ghz (900Mhz guaranteed).  This implies that it should have a beta at 28Mhz of something like 75, although it could be as low as 33.  Still, this is a lot better than a beta of 10 and they only cost $.08 each.  Not a bad deal.

I felt it was inelegant to use an emitter follower on the input.  I wanted the amp itself to present an input impedance high enough to prevent distortion caused by loading of the source.  (My source for this experiment is an HP8660C signal generator with 50 ohm impedance and is probably more forgiving than a one transistor oscillator would be.)      

I wanted to start by using a relatively large emitter resistor in order to make the DC equivalent base resistance (approximately the emitter resistor multiplied by beta) high enough to allow the bias resistors to be relatively high.  This combination will help give the amplifier a relatively high input impedance.  A perfect voltage amplifier has an infinite input impedance and zero output impedance - but we will settle for "high enough" and "low enough". 

We want to use low enough bias resistor values so that the current flowing through the bias resistors to ground is not significantly affected by base current going into the transistor, which will vary with the signal.  If the transistor was theoretically perfect and had an infinitely high beta, there would be no base current and we could just pick huge values for the bias resistors and they would then be a non-factor in the input impedance calculation.  However, there is a limit to how large we can make the emitter resistor and, therefore, the equivalent base resistance.   

So, to drive a stake in the ground and get things started, I chose an emitter resistor value of 20k.  Here's the circuit that results.

The blue voltages are DC bias values.


Choosing the other values follows fairly naturally from the emitter resistor value. 

Picking the emitter voltage:
Picking the bias voltage on the emitter will immediately determine two important characteristics of the circuit:

    1) the current that will flow through the collector and the emitter (within a couple of percent, they are the same), and 

    2) the maximum output voltage swing that is possible.  Transistors need current to make them work.  We could consult the device curves to see how much current we need to make the 5719 exhibit a decent beta, but the datasheet I have on that transistor doesn't include those curves.  So I decided to just get empirical about it.  I'll take what I can reasonably get using 20k for the emitter resistor.

The maximum theoretical voltage swing we could ever hope for in a simple circuit powered by 5 volts is, of course, 5 volts.  For a variety of reasons, we can't expect the output voltage to get all the way to the power supply rails in a one stage amplifier.  So we accept that we are going to use up some of the potential voltage swing to make the circuit work.  I chose to invest about 1.6 volts to apply to the emitter resistor.   This will create a collector/emitter current of about 1.6v/20,000ohms, which is 80 microamps.  Adding Vbe of .6 or .7 volts to these, we can see that we have decided that we want the base to be biased at about 2.3 volts.  We will design the ratio of the two bias resistors to produce 2.3 volts on the base.

Choosing the bias resistors:
Now let's turn our attention to the bias resistors.  In a perfect world, R1 and R2 form a voltage divider that sets the bias voltage on the base.  But in the real world, the equivalent base resistance is in parallel with R2, and it must be taken into account.  Let's refer to this equivalent base resistance (looking into the base) as Rbe (R base equivalent).  Let's refer to the parallel combination of R2 and Rbe as R2'.  It is calculated as R2' = R2 x Rbe/(R2 + Rbe).  But let's not get lost in calculations.  Let's do as much as we can by inspection. 

First we need to know the equivalent resistance of the base of the transistor.  As mentioned before, we can estimate it as being equal to beta times the emitter resistor (R3 in the circuit above).  So we can think of the equivalent base resistance as 20k x 50, assuming beta is at least 50.  This means the base presents an equivalent resistance of about 100k. 

So we already know some interesting things about R2.  We know that it will dominate if it is substantially less than 100k.  We also know that Rbe will predominate if we make R2 a lot larger than Rbe.  So there is not a lot of sense in making R2 a whole lot larger or a whole lot smaller than Rbe.

Now we find ourselves in a quandry.  Or, more correctly, in a tradeoff.  The tradeoff is this:  1) we want the value of the bias resistors R1 and R2 to be as high as possible in order to make the input impedance of the amplifier as high as possible.  On the other hand  2) we also want the bias resistors to be as small as possible so that the current flowing through them will be as high as possible - which will then mean the current drawn by the base of the transistor will be small in comparison and the base bias voltage will be relatively fixed.  If the base voltage varies too much as the base current changes, the waveform will be distorted.

Unless we are prepared to give up high input impedance or high fidelity, we are forced by this tradeoff to settle for values for R1 and R2 that are in the same general range as Rbe, the equivalent base resistance, - maybe in the range of 3 x Rbe down to 1/3 of Rbe.  The range will be determined at either end by distortion.  If we push the values of the bias resistors up we will eventually start to get signal distortion (because the base bias voltage will vary too much with the signal).  If we push the values down we will eventually start to load the source to the point where it starts to produce distortion or the signal level falls to an unacceptable level.

Whether the bias resistors are high or low, their ratio is chosen so that, in combination with the equivalent base resistance, the voltage divider function produces the base voltage we want.

The bias resistor values that result from this process are shown in the schematic above.  The input resistance of the circuit is the parallel combinaton of R1, R2, and Rbe.  That means the input resistance is 130k||120k||100k.  By inspection we know this is equal to about 40k (or about 1/3 of the average of the three resistances).  In fact, it calculates out to 38.4k.  So doing it by inspection isn't so bad.  This is about 700 times larger than the source resistance of 50 ohms, which is good.  However, this is not the whole story with respect to loading of the source.  The emitter bypass capacitor will change the impedance seen by the emitter and will result in a significant dynamic load being placed on the source.  But we will leave that discussion for a little later.

Now we have set the base bias voltage, which sets the emitter voltage, which sets the current that flows through the collector/emitter circuit and the collector resistor.  So we are most of the way there.

The next step is to pick the collector bias voltage.  The maximum possible output voltage swing will be from Vcc down to the emitter bias voltage.  We biased the emitter at 1.6 volts, so the maximum pk-pk voltage swing will be 5 volts - 1.6 volts = 3.4 volts.  This voltage swing can only be obtained if we bias the collector exactly in the middle between Vcc and Vemitter.  This means the the DC voltage drop across the collector resistor must be 1.7 volts.  We already know the collector current is 80 microamps, so we just calculate the collector resistor as:  Rcollector = 1.7v/80ua = 21.25k.  I used 22k.  We want this stage to have a lot of gain.  So, In general, we want the collector resistor to be as large as possible in order to get as much gain as possible.  However, if we make it any larger we will sacrifice voltage swing.  Likewise, if we reduce it we will lose voltage swing (or else we will have to re-bias the circuit by changing the R1/R2 ratio) and gain.

Now we have to pick values for the capacitors.  I picked the coupling, C1 and C3, without much thought.  I made them both .1uf.  At 28 Mhz they have low reactance, which is what we want.  If we really cared about phase shift through the amplifier, we would have to pay more attention to them. 

This leaves only the emitter bypass capacitor, C2, to pick.  This is a little trickier.  If we use too low of a value we will sacrifice gain.  If we use too high of a value, we will lose output signal level and start to see distortion due to source loading.  A higher value means lower reactance.  This means the equivalent base impedance at 28Mhz will, at some point, be so low that it will start to load down the source and cause its output to drop and eventually to distort.  I used an initial value of .1uf and then observed that the input signal Vgen had dropped some 10% or so from its open circuit value, so I know I can't make C2 much, if any, higher. 

Let's have a look at how the circuit performs by using a simulator.  I recently found 5Spice and like it.  I recommend it.  The free version is adequate for what we are doing here.

Here is the simulator output, showing the input voltage Vgen (in red) and the output voltage Vout (in blue). 


The source voltage is set at 50 mv peak to peak.  Yet we can see that it has dropped to about 45 mv (using the scale on the left side and the red trace).  We can also see that it is no longer exactly symmetrical around zero volts.  This tells us that it has been distorted somewhat because the energy in the positive half cycle is slightly less than the energy in the negative half cycle.  This indicates that the input impedance is slightly lower than we would like (causing source loading) or the transistor is in a very non-linear region.  We might be able to alleviate this some by reducing the value of C2.

By examining the output voltage in blue using the scale on the right side, we see that it is about .8 volts pk-pk.  So the practical gain is 800mv/50mv = 16.  We need a gain of 100.  So the circuit fails rather miserably.  The reason it fails is that the transistor is exhibiting a very low beta.  The reason for that is that we are operating it at such a low current level - it just has very little little current gain under this condition.

So we conclude that we must crank up the collector/emitter current high enough to get a decent beta out of the transistor.  A device curve would be helpful, but from experience I know the transistor needs a milliamp or two.

Taking into account what we have learned about the circuit so far, I changed it to this:

Which resulted in this performance:

Notice that we have reached our design goal.  The output waveform swings from -.2 volts to +5.2.  Notice also that it contains very little distortion, as evidenced by its symmetry around the midpoint voltage of 2.5. 

The salient points of the design are these:

1)  Most importantly, I gave up on the 5 volt circuit and used 12 volts for Vcc. 

2)  I used a 600 ohm emitter resistor to set the collector/emitter current at 1.13v/600 ohms = 1.9 ma.  This gets the transistor transisting enough to exhibit a decent beta and gives us the gain we need. 

3)  The emitter bypass capacitor has been reduced from .1uf to .0005uf.  This reduced the dynamic loading on the source, which increased the output and reduced source loading related distortion.

4)  The collector bias voltage is set mid point between Vcc and Vemitter.  We have more voltage swing available than we need - this makes the circuit more tolerant of component value errors and drift as well as avoides distortion.

5) Rload1 and RLoad2 reference the output waveform to 2.5 volts, the center of the 5 volt range of the CMOS digital parts.

6) No load capacitance has been taken into account.


As far as it goes, all looks well with this circuit.  But there is a problem.  It does not like any capacitive loading on the output.   Watch what happens when we assume only 3pf of load capacitance.

The output has been cut down to a 2.5 volt swing (blue line, right side scale).   However, the swing appears to be symmetrical, so at least we haven't introduced any noticeable distortion.

We are going to have to add an emitter follower to isolate, or buffer, Q1 from the load.

Which I did, using the circuit below.

However, this circuit just doesn't quite cut it.  I used every trick I know to increase the gain but it just falls a bit short, as you can see from this simulation output.  I was frustrated because we were so close to success.  But I could not find any way to get the gain up enough to make it meet our needs.  At this point we could test a batch of 2N5719s for fT and find one that is on the high end and use it.  This can be done simply by testing for beta at 28Mhz.  We could also switch to a better transistor.  I think there are some higher performance transistors that would push the amplifier's performance up enough to make it meet our needs.  But the transistor we are using is only an $.08 item, so using several of them rather than an exotic surface mount transistor seems like is a pretty good solution.  It also yields instant gratification since I can keep going rather than waiting for another order of transistors to arrive from Mouser.

This output waveform would probably actually work ok to drive a CMOS logic chip, but it's not very satisfying and it is not at all robust.  Variations in component values and stray capacitances will probably mean this circuit is going to be "touchy" and not very reliable.

So I felt the need to add another gain stage so we can wind up with a circuit that easily meets our requirements and is less likely to be adversely affected by errors and variations in component values, variations in beta, and temperature effects.  This is one of the great joys of Ham Radio:  we are not forced to find the absolute minimalist solution - as we would be if this design was for a commercial product that would be produced in volume.  We are also not forced to settle for marginal solutions that just barely work but leave us feeling unsatisfied.  Imagine walking across a bridge that wobbles and just barely meets the requirements.  Compare that feeling to walking across a bridge that has been overdesigned so that there is plenty of excess strength.  It gives us confidence that it will still work even if it is subjected to a more harsh environment that originally expected.  So let's make the circuit a solid one that leaves us feeling confident and satisfied.

Here's the circuit I came up with.

The gain stage I added just kicks it up by a factor of two or so.  Notice that the emitter resistor is not bypassed.  As a result, the input impedance is high (which is very good) and the gain is simply Rcollector/Remitter.  Unfortunately, collector circuits are very sensitive to loading so we still need an emitter follower.  The second stage gives us plenty of gain and the emitter follower has the ability to drive a reasonable load, whether resistive or capacitive. The two together give us a pretty good circuit.  There are no stability issues because there is no feedback and there are no inductive elements.  It's all very straightforward and solid.

One interesting design element is that the emitter follower is dc coupled.  That means that the bias level of the collector of the second gain stage sets the base bias voltage for the emitter follower.  I did this to avoid the coupling capacitor and the typical upper and lower bias resistors, which would have presented more of a load to the second gain stage.   

This circuit is a keeper.  It produces the required output with little distortion even though I have strewn a few stray capacitances around and have asked the circuit to drive a load capacitance as high as 15 pf. 

Here's the simulation output at room temp with 15 pf of load capacitance.  It does not vary discernibly at either -25 degrees C or 100 degrees C.


The circuit is pretty impervious to various loads.  Below is the output result with 1 pf of load capacitance.

The circuit works well with either light loading or fairly heavy loading.  The gain can be tweaked slightly by tweaking R8 or R7 to accommodate the actual load applied to the circuit.  Small changes in these values will not require re-biasing.  

The next step is to build this and see how close the simulation is.  Which I will do.  But I'm pretty confident that this circuit is robust and these results will be attainable.  I'll update this after building and testing it.


Another solution:  a tuned collector circuit.

The gain of a common emitter amplifier is a direct function of the collector impedance and the transistor beta.  So we can increase the gain by increasing this impedance.  However, if we do this by increasing the collector resistor we have to reduce the amount of current running through the collector or else the transistor will saturate as the collector voltage moves down.  As we saw earlier, if we reduce the collector current too much, the transistor will have insufficient beta and we start losing gain again.  But we can increase the collector impedance at the operating frequency without increasing the collector resistor by adding an LC tuned circuit to the collector circuit.  Here's the schematic.


L1 and C3 form the tuned circuit.  The actual values to make the circuit resonant at 28 Mhz are 35pf and 1uh.  But the circuit becomes a bit unstable when we make the tuned circuit resonant right at 28 Mhz.  So I tuned it off frequency a bit (downward) to make it stable, yet its impedance at 28Mhz is still high enough to give us enough gain to meet our goals without adding a second gain stage.  I suppose it comes down to whether you like inductors better than transistors. 

R5 is an attempt to model a real world inductor.  If the circuit shows any tendency toward instability, this resistance can be increased by adding a resistor in series with the inductor, which will reduce the circuit's Q and should calm things down.

Here's the simulation output.


I hope to get around to building this one soon too, and will report on it when I do.


Home   Homebrew Stuff